As digital electronic circuits become increasingly faster in speed of operation, a need exists for a clock signal with an accurate fifty percent duty cycle for clocking data and for other purposes. Such clock signals are required at frequencies in a range of up to several hundred MHz. To obtain a clock signal with a precise and nonvariable frequency, others have typically used a crystal oscillator. In many digital circuits, such as microprocessors, a clock signal having a fifty percent duty cycle with less than a couple percent error is required. At high frequency, if the duty cycle is not extremely accurate, such as within a percent of fifty percent, circuit errors can be generated due to timing errors. Others have typically obtained an accurate fifty percent duty cycle by using a crystal having a frequency which is twice the frequency of the desired clock signal. A divide by two counter is used to divide the crystal's frequency to a frequency having a fifty percent duty cycle. Several disadvantages exist with this type of clock generator circuit. As a crystal's frequency is increased, so is the cost of the crystal if frequency accuracy is required. Therefore, when a clock frequency in the several hundred MHz range is desired, the use of an expensive crystal having twice the desired frequency typically becomes cost prohibitive. Further, the use of a high frequency signal is generally problematic. Others not using a double frequency oscillator typically reduce system frequency in order to meet a required duty cycle tolerance.